http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007027677-A

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filingDate 2005-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2007-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2007027677-A
titleOfInvention Semiconductor device
abstract PROBLEM TO BE SOLVED: To make the operation speed in a CMOS circuit the same, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to the difference in carrier mobility. This area imbalance has hindered the improvement in the degree of integration of semiconductor devices. A semiconductor layer (SOI layer) provided on an SOI substrate and a gate electrode provided on the SOI layer, and a depletion layer having a thickness due to a work function difference between the gate electrode and the SOI layer is provided. At least one MOS transistor which is normally off by setting the film thickness of the SOI layer so as to be larger than the film thickness of the SOI layer is provided. [Selection] Figure 1
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8329520-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8643106-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009124653-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009076890-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013012768-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018148244-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012138575-A
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Total number of triples: 30.