http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006287238-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
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filingDate 2006-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21747acfb77b0d181ab4dff0d66658d4
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publicationDate 2006-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2006287238-A
titleOfInvention Flip-flop circuit and static RAM using the same
abstract A semiconductor integrated circuit having a multilayer structure in which wirings of an upper layer thin film transistor (TFT) and a lower layer transistor are formed with high yield is provided. First and second TFTs are provided on first and second transistors, and the gate wiring of the first transistor and the drain of the second transistor are connected via the gate wiring of the first TFT. The gate wiring of the second transistor and the drain of the first transistor are electrically connected via the gate wiring of the second TFT, and the drain of the first TFT and the gate of the second TFT are connected. The wiring is electrically connected via the first wiring, and the drain of the second TFT and the gate wiring of the first TFT are electrically connected via the second wiring. [Selection] Figure 2
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8049253-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015111706-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8841730-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8470688-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013161878-A
priorityDate 1993-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H05136167-A
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Total number of triples: 30.