| abstract |
A chip size package structure having a preferable heat dissipation effect, reduced contact resistance, improved yield and reliability, and a method of forming the same are provided. A wafer on which dies are formed is diced, a diced die 101 is picked and placed on a base 100, a first material layer 106 is filled between dies on the base, and a dielectric layer 107 is formed. Forming a first opening that exposes a portion of the lead wire 103 of the die, forming a first conductive material layer 109 on the dielectric layer, and filling the opening in the die 1 to form a second material layer 110 is formed and patterned, the first conductive material is exposed to form a second opening, and a solder ball 112 is calcined into the second opening to obtain a chip size package structure. [Selection] Figure 7 |