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filingDate 2003-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99efb7fa71176d72d21b469a8f9c24a5
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publicationDate 2004-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2004260001-A
titleOfInvention Method for manufacturing semiconductor device
abstract Provided is a method of manufacturing a semiconductor device capable of suppressing an increase in contact resistance, a decrease in yield, and a decrease in reliability even when an SiOC film is used as an interlayer insulating film. In a dual damascene method of a via-via method, after forming a via hole and a wiring groove, an exposed portion of an SiN film, an exposed portion of an SiC film, and an exposed portion of an SiC film are removed by etching. As a result, the via hole 10 reaches the Cu wiring 2 and the wiring groove 13 reaches the SiOC film 4. Further, the reaction product 14 mainly adheres to the side wall of the wiring groove 13. Although the reaction product 14 adheres to other portions, the amount of the reaction product 14 attached to the side wall of the wiring groove 13 is the largest. Subsequently, the inside of the via hole 10 and the wiring groove 13 is subjected to oxygen plasma processing. As a result of this oxygen plasma treatment, the reaction product 14 is removed. [Selection diagram] FIG.
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