http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004079770-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-146 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-339 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-148 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 |
| filingDate | 2002-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9cd393348be700b936a3beb3db65aa72 |
| publicationDate | 2004-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2004079770-A |
| titleOfInvention | Insulated gate field effect transistor, method of manufacturing the same, solid-state imaging device, and method of manufacturing the same |
| abstract | Provided are an insulated gate field effect transistor that suppresses the occurrence of a shutter step and suppresses the occurrence of punch-through and injection, a solid-state imaging device using the same, and a method of manufacturing the same. An insulated gate field effect transistor in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region are formed in the semiconductor substrate on both sides of the gate electrode. 30, a P-type first diffusion layer 12 formed on the semiconductor substrate 11 at a position deeper than the source region 33 and the drain region 34; and a semiconductor substrate 11 formed at a position deeper than the first diffusion layer 12 on the semiconductor substrate 11. And a P-type second diffusion layer 13 having a higher concentration than the first diffusion layer 12 and constituting an output circuit of a solid-state imaging device. Some or all can be used. [Selection diagram] Fig. 1 |
| priorityDate | 2002-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.