| abstract |
[PROBLEMS] To improve the degree of integration by reducing the influence of the back bias effect, to increase the ratio of the capacitance between the floating gate and the control gate without increasing the occupied area, Semiconductor storage device with no characteristic variations. SOLUTION: A memory cell including a semiconductor substrate, an island-like semiconductor layer, a charge storage layer formed on the entire periphery or a part of a side wall of the semiconductor layer, and a control gate formed thereon, and the memory. A gate electrode formed at one end of the cell and arranged in series with the cell, wherein at least one of the charge storage layer and the gate electrode is formed in a recess formed in a side wall of the island-shaped semiconductor layer; A semiconductor memory device in which a part is disposed and at least one of the control gates is disposed in a recess formed in a side wall of the charge storage layer. |