| abstract |
A simplified dual damascene method using chemical mechanical polishing to form an integrated circuit is provided. A method is provided for forming planarized structures, metal line interconnects, interconnects, and via contacts without the problem of dimple formation. The method includes depositing first and second insulating layers on a substrate, forming an opening through the second insulating layer, depositing a conductive metal in the second insulating layer, and removing excess conductive metal. Is removed, a third insulating layer is deposited, patterned and etched to form openings over the conductive metal lines, a layer of plasma-polymerized methylsilane is deposited and exposed to ultraviolet light to form the oxide. Forming a barrier conductive layer lining the trenches and vias, shielding ultraviolet light at the trenches and via openings, removing unexposed portions from the trenches and via openings, depositing a barrier conductive layer lining the trench and via areas. The layer is deposited and the excess metal layer is planarized by CMP without creating metal depressions. |