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filingDate 2018-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83ee57e7824fd8a0cd4420f9685fe5b2
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publicationDate 2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-3685427-A1
titleOfInvention Method to reduce pore diameter using atomic layer deposition and etching
abstract Methods for making well-controlled solid state nanopores and solid state nanopore arrays well controlled by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and an engraving. One or more elements are formed in a thin layer deposited on an upper side of a substrate. A dielectric material is deposited on top of the substrate having the element or elements in the thin layer. An etching process is then used to etch a portion of the dielectric material deposited on top of the substrate having the element (s) in the thin layer. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the elements until a well-controlled nanopore is formed through the thin layer on the substrate.
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Total number of triples: 29.