| abstract |
A vertical isolated gate FET transistor according to the invention is integrated in the front end of line of a semiconductor chip. The transistor includes a modified version of a buried power rail and back side TSV (Through Semiconductor Via) connection known for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. As opposed to a standard power rail/TSV combination, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well furthermore comprises a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa. |