| abstract |
The method comprises the steps of 1) producing first and second blanks (EB1, EB2) by laminating insulating and conductive inner layers (PP, CP, El) on copper plates forming a base (MB1, MB2), at least one electronic chip (MT, MD) being sandwiched between the blanks, said blanks being produced such that their upper lamination surfaces have matching profiles, 2) stacking and fitting the blanks via their matching profiles, and 3) press-fitting the blanks to form a laminated sub-assembly for an integrated power electronics device. The method uses IMS-type techniques. |