| abstract |
A memory device according to one embodiment includes: a first memory chip including a first circuit, first and second terminals; a second memory chip including a second circuit and a third terminal; and an interface chip including first and a second voltage generation circuits. The second memory chip is provided above the first memory chip, and the interface chip is provided below the first memory chip. A first end of the first terminal is connected to the first circuit and a second end of the first terminal is connected to the first voltage generation circuit. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generation circuit. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generation circuit via the second terminal. In a direction perpendicular to a surface of the first memory chip, the third end overlaps with the sixth end, without overlapping with the fourth end. |