| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e54ce8ac84bd4ca6f6f8d9a2ef406f0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_429245cd41c2f78dfbb5d4075baae975 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32137
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23F1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28114 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 |
| filingDate |
2017-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04ffd9023604c1b86258a03ecfa7501b |
| publicationDate |
2018-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3333888-A1 |
| titleOfInvention |
Semiconductor device and fabrication method thereof |
| abstract |
A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate (300) including a first region (I) for forming a first transistor and a second region (II) for forming a second transistor, the first transistor having a working current less than the second transistor. The fabrication method further includes forming a gate electrode layer on the base substrate; etching the gate electrode layer to form a first gate electrode (231) in the first region; after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode (232) in the second region, with the second gate electrode (232) having an undercut structure; forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain region in the base substrate on both sides of the second gate electrode. |
| priorityDate |
2016-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |