| abstract |
An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) (e.g., first wafer level die), and a second die (208) (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer (203), a first set of interconnects (280) located in the first inorganic dielectric layer, a second dielectric layer (202) different from the first inorganic dielectric layer, and a set of redistribution metal layers (230,240,250,260) in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects (280). |