| abstract |
A first semiconductor element (4) is mounted on a base plate (1), and is in a sealed state by the periphery thereof being covered by an insulation member (16), and the upper surface thereof being covered by an upper insulation film (17). An upper wiring layer (20, 24) formed on the upper insulation film (17), and the lower wiring layer (33, 37) formed below the base plate (1) via lower insulation films (31, 34) are connected by conductors (43). A second semiconductor element (40) is mounted exposed, being connected to the lower wiring layer (33, 37). |