http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1102315-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2c78d80e9d323ad7c79518c80e0b8d16 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76865 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304 |
| filingDate | 2000-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fabf330e909bc46a4272d3c2335d189d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3339e5d8ce405a769c5387293ea470e4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5864ca4913c602c0a55011ad0ab11ad2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7878e5961d9b1dec2267590dc241db18 |
| publicationDate | 2001-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1102315-A2 |
| titleOfInvention | A method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
| abstract | A new method to prevent copper contamination of the intermetal dielectricnlayer during via or dual damascene etching by forming a capping layer over thenfirst copper metallization is described. A first copper metallization is formed in andielectric layer overlying a semiconductor substrate wherein a barrier metal layernis formed underlying the first copper metallization and overlying the dielectricnlayer. The first copper metallization is planarized, then etched to form a recessnbelow the surface of the dielectric layer. A conductive capping layer is depositednoverlying the first copper metallization within the recess and overlying thendielectric layer. The conductive capping layer is removed except over the firstncopper metallization within the recess using one of several methods. Annintermetal dielectric layer is deposited overlying the dielectric layer and thenconductive capping layer overlying the first copper metallization. A via or dualndamascene opening is etched through the intermetal dielectric layer to thenconductive capping layer wherein the conductive capping layer prevents copperncontamination of the intermetal dielectric layer during etching. The via or dualndamascene opening is filled with a metal layer to complete electrical connectionsnin the fabrication of an integrated circuit device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102007009912-B4 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7867889-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102007009912-A1 |
| priorityDate | 1999-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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