http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0694959-A2

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filingDate 1990-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_48a7878c1b7ca46e9eec7ad4d2a28f2d
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publicationDate 1996-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0694959-A2
titleOfInvention Trench etching in an integrated-circuit semiconductor device
abstract In the manufacture of semiconductor integrated circuit devices, semiconductor regions (14) such as, e.g. doped regions or tubs are separated by an etched trench (16) which is self-aligned with respect to such regions on account of the presence of an etch-resistant layer overlying the regions during etching. In accordance with preferred processing of the invention a first layer (12) is formed alongside the trench to be etched, a spacer second layer (13) is formed alongside the edge of the first layer, and a third layer (15) is formed abutting the spacer. The spacer is etched away while first and third layers remain in place, and the trench is etched in the space between the first and third layers. A preferred etchant comprises CF₃Br and oxygen.
priorityDate 1989-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.