http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0559323-A2

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_040ec81c891acc3f3186f56cb99cf161
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 1993-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d2a37c343c275daacbc2abf620572e3
publicationDate 1993-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0559323-A2
titleOfInvention Improved method of patterning a submicron semiconductor layer
abstract An interlevel dielectric layer (24,26) is formed over the surface of the integrated circuit. A substantially planarizing layer (30) is formed over the interlevel dielectric layer (24,26). A photoresist layer (32) is formed and patterned over the planarizing layer (30). The planarizing layer (32) is etched to form openings (34) exposing selected portions of the interlevel dielectric layer (26,24), wherein each opening (24) has substantially the same lateral dimensions. The photoresist (32) and planarizing layers (26,24) are then removed. The interlevel dielectric layer (24,26) is etched in the openings to expose portions of the underlying integrated circuit.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9704319-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0019534-A1
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priorityDate 1992-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 28.