http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0439727-A2

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4ddcb273a108a5d8472b335280098e06
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23F4-00
filingDate 1990-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a050f9f2d94591e19fcd02f825ce15a5
publicationDate 1991-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0439727-A2
titleOfInvention Process to make grooves in silicon substrates for high density integrated circuits
abstract In order to produce trench structures (3) with vertical, smooth side walls (4) and straight, flat trench bottoms (5) in silicon substrates (1), the reactive ion etching is carried out in a triode single-disc plate reactor using an etching mask (2) which preferably consists of SiO 2 and with exclusively an etching gas atmosphere consisting of chlorine in the low pressure range. Compared to known ion etching processes, a carbon-free, simple etching chemistry with acceptable etching rates is used here. The method is used in particular for the production of DRAMs with cell concepts of more than 4 Mbits.
priorityDate 1990-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 23.