http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0252450-A2

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filingDate 1987-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80a9dcd8843c919784e9cd8cd0e9340a
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publicationDate 1988-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0252450-A2
titleOfInvention Integrated circuit isolation process
abstract A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-4340226-C2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5807784-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6008526-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0330989-A3
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priorityDate 1986-07-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 32.