| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a2bcaf91101a370a3d64e3190366357f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-975
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 |
| filingDate |
1994-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c73ca80de79f44c397fa60aa50ca78d9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9aeb8b6a01b8012308f167531ad4815 |
| publicationDate |
1996-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-4433846-A1 |
| titleOfInvention |
Method of making a vertical integrated circuit structure |
| abstract |
The method involves preparing a first substrate (1) with one or more layers (5) with circuit structures and at least one metallised plane (6) near a first main surface. A mask film (8) for subsequent etching of dielectric films is applied to the side of the main surface. Through holes (10) are opened through the mask and first circuit structure layers. The first substrate is connected to an auxiliary substrate (12) on the side of the first main surface. The first substrate is thinned on the side opposite the first main surface. A second substrate (130 is prepared with second main surface, circuit structure layer (15) and metallised plane (16). The substrates are connected by bringing together their sides opposite their main surfaces with some adjustment. The auxiliary substrate is removed. The through holes are opened as far as the second metallised plane using the first substrate's mask as an etching mask. A conducting connection between the metallised planes is formed via the through holes. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19946715-C1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6448174-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6444493-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19818968-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19818968-C2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6548391-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19813239-C1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-9949509-A1 |
| priorityDate |
1994-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |