| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66363
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41741
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41725
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66348
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-76 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-485 |
| filingDate |
2008-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70c623f2a66a7082cd62d84aa6a8f07e |
| publicationDate |
2010-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-112008002270-T5 |
| titleOfInvention |
MOS structures with a lower contact resistance and method for their production |
| abstract |
A method of making a MOS structure (100), the method comprising the steps of: Providing a semiconductor substrate (106); Forming a gate stack (146) on the semiconductor substrate; Forming a doped region (116) in the semiconductor substrate in an aligned manner with the gate stack; Forming adjacent contact lands (186) extending from the doped region; Forming a metal silicide layer (126) on the contact lands; and Producing a contact (122) on at least a portion of the metal silicide layer on at least one of the contact lands. |
| priorityDate |
2007-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |