| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2020-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68298e8e373a8c0ab442b9ee65fd5848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_630d96fc25174c40f48f1cf9c2a530a3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aabf5319dbf359c62231ca657aee5aa9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c05f818a51524a26178cd30e9839951a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b7320a69bae6df58ddfa73eed77c847 |
| publicationDate |
2021-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102020114860-A1 |
| titleOfInvention |
TRANSISTOR GATES AND METHOD OF MAKING THEM |
| abstract |
An apparatus includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, wherein a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper Portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer. |
| priorityDate |
2020-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |