| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0928
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76892
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28556
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2020-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_247d53b2e422209cf7249ee5471f2ee7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff47bb0f61035fdc473412f9fbd6eb58
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c842b8496a8c73d3b10dd87deba7da0a |
| publicationDate |
2021-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102020113628-A1 |
| titleOfInvention |
SEMICONDUCTOR DEVICE AND METHOD |
| abstract |
One method of the embodiment includes: forming a gate stack over a channel region; Building a source / drain region adjacent to the channel region; Depositing a first ILD layer over the source / drain region and the gate stack; Forming a source / drain contact through the first ILD layer to physically contact the source / drain region; Forming a gate contact through the first ILD layer to physically contact the gate stack; Performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source / drain contact and the first ILD layer; Forming a first conductive feature physically in contact with the first sidewall and a first top surface of the source / drain contact; and forming a second conductive feature physically in contact with the second sidewall and a second top surface of the gate contact. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022359379-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11764149-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11424182-B2 |
| priorityDate |
2020-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |