| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66689
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2020-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d8743ddd7692b5297978a5360cc82501
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_129afe943068d4f66cc519747a0ddbd5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9653c4283fde0d28d58bba5c270655b8 |
| publicationDate |
2021-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102020108652-A1 |
| titleOfInvention |
FIELD PLATE AND INSULATION STRUCTURE FOR HIGH VOLTAGE COMPONENTS |
| abstract |
An integrated chip has a field plate overlying an isolation structure. A gate electrode lies over a substrate between a source region and a drain region. An etch stop layer extends laterally from a top surface of the gate electrode to a front side of the substrate. The etch stop layer lies over a drift region which is arranged between the source region and the drain region. The field plate is disposed within a first interlayer dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the ILD layer to a top surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front side of the substrate to a point below the front side of the substrate. The insulation structure is arranged laterally between the gate electrode and the drain region. |
| priorityDate |
2020-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |