http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102019103481-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 |
| filingDate | 2019-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_641271c29858c8ca6f63d5157d045820 |
| publicationDate | 2021-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102019103481-B4 |
| titleOfInvention | Via sizes to reduce the risk of bridging and improve performance |
| abstract | Semiconductor device with: a first gate structure (250), a second gate structure (251) and a third gate structure (260), each extending in a first direction (Y); a first gate via (VG1) which is arranged on the first gate structure (250), wherein the first gate via (VG1) has a first size (401); a second gate via (VG2) disposed on the second gate structure (251), the second gate via (VG2) having a second size (402) that is larger than the first size; a third gate via (VG3) disposed on the third gate structure (260), the third gate via (VG3) having a third size (403) that is smaller than the second size but larger than the first size; a first source contact (320) which is arranged adjacent to a first side of the first gate via (VG1); a first drain contact (321) which is arranged adjacent to a second side of the first gate via (VG1) which is opposite to the first side; and a second drain contact (330) which is arranged adjacent to a first side of the third gate via (VG3); in which the first gate, the first gate via (VG1), the second gate and the second gate via (VG2) are components of a first circuit cell, the third gate and the third gate via (VG3) are components of a second circuit cell, and the first circuit cell and the second circuit cell are different types of circuit cells. |
| priorityDate | 2018-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 49.