| abstract |
Semiconductor device comprising: a substrate (110); a channel layer (120) disposed on the substrate (110); a barrier layer (130) disposed on the channel layer (120), the barrier layer (130) having a depression (R), the barrier layer (130) having a portion below the depression (R), and the portion having a thickness ( d2); a source (S) and a drain (D) disposed on the barrier layer (130); a charge trapping layer (220) covering the bottom surface of the recess (R); a ferroelectric material layer (230) disposed on the charge trapping layer (220); and a gate (250) disposed over the ferroelectric material (230). |