| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_59c820ad08f8533c7440ae1d9235b168 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41766
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065 |
| filingDate |
2016-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_811e1e6dc6a715c16328af19e34d5be9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc2f4b4cdb6c8c91f3e6f0550423080e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e32e8632a145817b8862549ec53f7c2f |
| publicationDate |
2017-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102016106580-A1 |
| titleOfInvention |
Integrated transistor arrangement with a plurality of vertical transistors |
| abstract |
A transistor arrangement is disclosed. The transistor arrangement comprises a semiconductor body having a plurality of semiconductor layers which are stacked between a first surface and a second surface of the semiconductor body; a plurality of transistors, each having a load path and a control terminal. The load paths of the plurality of transistors are connected in series between a first load terminal and a second load terminal of the transistor arrangement. Each of the plurality of transistors is at least partially integrated in a corresponding one of the plurality of semiconductor layers, and the transistor arrangement has a control terminal which is connected to the control terminal of a first transistor of the plurality of transistors. |
| priorityDate |
2016-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |