http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102015106185-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4916 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66568 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2015-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f24dda2e753ac3b6f6f0bbe79c0d7d77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c9d07e695abcf0db4a1a204f1f4ff98 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1a5144f100913c9d943a61c7e61040e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d14391619d27af0acbbcfe50854e4ab9 |
| publicationDate | 2020-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102015106185-B4 |
| titleOfInvention | Semiconductor structure and method for processing a carrier |
| abstract | Semiconductor structure (100), comprising: a first source / drain region (102sd) and a second source / drain region (102sd); a body region (102b), which is arranged between the first source / drain region (102sd) and the second source / drain region (102sd), the body region (102b) having a core region (102c) and at least one edge region (102e), which the Core area (102c) at least partially surrounds; a dielectric region (102i) which is adjacent to the body region (102b) and is designed to limit a current flow through the body region (102b) in a width direction of the body region (102b), the at least one edge region (102e) between the core region ( 102c) and the dielectric region (102i); and a gate structure (104) configured to control the body region (102b); wherein the gate structure (104) is configured to provide a first threshold voltage for the core region (102c) of the body region (102b) and a second threshold voltage for the at least one edge region (102e) of the body region (102b), the first threshold voltage being less than or equal to that second threshold voltage is wherein the gate structure (104) has a gate region (104a, 104b) and a dielectric layer which is arranged between the gate region (104a, 104b) and the body region (102b), and wherein the gate area (104a, 104b) has a first portion that at least overlaps the core area (102c) of the body area (102b) and at least a second portion adjacent to the first part, which at least overlaps the at least one edge region (102e) of the body region (102b). |
| priorityDate | 2014-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.