| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-761
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66704
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2014-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78e39ab23412da5e8687cd7d49b61423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39fdaba8826e38a4bd75e15831007bce
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a39e8b1d70dea2ec3b6a25b3458bc38f |
| publicationDate |
2015-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102014113087-A1 |
| titleOfInvention |
Semiconductor device, integrated circuit and method of manufacturing a semiconductor device |
| abstract |
A semiconductor device comprises a transistor (5) in a semiconductor substrate (10) having a first main surface (110). The transistor includes a source region (201), a drain region (205), a channel region (220), a drift region (260), and a gate electrode (210) adjacent to at least two sides of the channel region (220). The channel region (220) and the drift region (260) are arranged along a first direction parallel to the first main surface (110) between the source region (201) and the drain region (205). The semiconductor device further includes a conductive layer (270) below the gate electrode (210) and insulated from the gate electrode (210). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102016113393-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10381477-B2 |
| priorityDate |
2013-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |