http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102013108147-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-085 |
| filingDate | 2013-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c871888b68c886c8f8a3b46db897a93c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e847fedc93ab105d971a49cf02f05c53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08da4b1e5f68c892cdc012c587f1859d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cb4c55c6cc2d66163029d9b97180f50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd8d43362ded6083a0dddb71ec7d6ea7 |
| publicationDate | 2016-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102013108147-B4 |
| titleOfInvention | Method and structure for vertical tunnel field effect transistor and planar devices |
| abstract | A method of forming a semiconductor structure comprising a tunnel field effect transistor, TFET, the method comprising: Providing a semiconductor substrate (110) having a first region (112) and a second region (114); Forming a semiconductor mesa (120) on the semiconductor substrate (110) in the first region (112); Applying a first implantation (124) to the semiconductor substrate (110) in the first region (112) and the semiconductor mesa (120) to form a drain (126) of the TFET, wherein the drain (126) of the TFET is a first type of conductivity having; Forming a first dielectric layer (130) on the semiconductor substrate (110) in the first region (112) and sidewalls of the semiconductor mesa (120); Forming a second dielectric layer (134) and a conductive layer (136) on the first dielectric layer (130); Patterning the second dielectric layer (134) and the conductive layer (136) to form a first gate stack (138) in the first region (112); Applying a second implantation (144) to the semiconductor substrate (110) in the second region (114); Forming a third dielectric layer (150) on the second dielectric layer (134); Applying a third implant to the semiconductor mesa (120) to form a source (152) of the TFET, the source (152) of the TFET having a second type of conductivity opposite the first type of conductivity; and Forming an intermediate layer (132) on the semiconductor substrate (110) in the second region (114), wherein forming a second dielectric layer (134) and a conductive layer (136) comprises forming the second dielectric layer (134) and the conductive layer (136) on the intermediate layer (132), structuring the second dielectric layer (134) and the conductive layer (136) pattern the second dielectric layer (134) and the conductive layer (136). |
| priorityDate | 2013-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.