| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-68 |
| filingDate |
2013-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac1319602743c6005a34cb0f12030f35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f59bc4487c8f6f2f733f3316d4e632df
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_994f3e3f0b4c4094c3591677ce1faae1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52de0d49eb322d5c5a38920ace7977fb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f3c97d8cb3114cf9c8349181c60fa9b |
| publicationDate |
2014-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102013108147-A1 |
| titleOfInvention |
Method and structure for vertical tunnel field effect transistor and planar devices |
| abstract |
The present disclosure provides an embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; applying a first implant to the semiconductor substrate and the semiconductor mesa to form a drain of a first type of conductivity; forming a first dielectric layer on the semiconductor substrate and sidewalls of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming a source on the semiconductor mesa having a second type of conductivity that is opposite to the first type of conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET. |
| priorityDate |
2013-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |