| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_69a4ae662cd6a46490ee45a70e85dc39 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16146
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-81
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05009
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-131 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-04 |
| filingDate |
2006-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95a8122ce1ffdd1fbb978f7d2877d9f2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ef548b8e0365bfacf53da689a342d27 |
| publicationDate |
2008-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102006049476-A1 |
| titleOfInvention |
Semiconductor chip, semiconductor chip stack and method for stack mounting of semiconductor chips |
| abstract |
Of thenInvention comprising a semiconductor chip, semiconductor chip stack and anMethod for stack mounting of semiconductor chips with an activenFront side, which are provided with circuit elements including contact padsnis, arranged in the region of the contact pads viasnin the form of vias on the active front and on the backnin the form of metal plugs exposed and the metal plugs with anLotmaterial are concerned, the object is based,nwhile maintaining the structuring of the via withnonly one mask the galvanic deposition of solder on the thinned wafernto avoid. This is solved by the soldering materialnthe active front in the form of solder balls applied to the metal plugsnand the spaces between themnbetween the solder ballsnbe filled on the semiconductor wafer with a potting compound. |
| priorityDate |
2006-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |