http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102005063129-A1

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76237
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
filingDate 2005-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_068ef1c9f20bab60ed341f77fee3540a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a45037e699744f8bfab98507ece818e
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publicationDate 2007-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-102005063129-A1
titleOfInvention Trench isolation structure for a semiconductor device with reduced sidewall strain and method of making the same
abstract BynForming a non-oxidizable coating in isolation trenches isnthe generation of a compressive strain significantly reduced, whereinnin illustrative embodimentsnSilicon nitride is used as a coating material. To this endnbecomes the etching behaviornof silicon nitride clearly based on a suitablensurface treatmentnmodified, thereby providing a high level of material integrity during ansubsequent etching processnto remove unmodified areas of the silicon nitridenwhich is also used as an efficient CMP stop layerncan.
priorityDate 2005-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 26.