http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115166461-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_386edcf52001ff8bc7805d863b0f0d95 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-129 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R1-203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2601 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2642 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-20 |
| filingDate | 2022-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3c9eb442489c1db52e1c623df519f055 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_893f491d1163907897ae91ccda9a23f5 |
| publicationDate | 2022-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-115166461-A |
| titleOfInvention | Test device structure unit, parallel test device structure and wafer |
| abstract | The invention provides a test device structure unit, a parallel test device structure and a wafer. When using the traditional MOS device test structure to test the electrical performance of the wafer, such as HCI or NBTI test, 4 SMUs are required at all levels of the MOS device, and the test efficiency is low. The test device structural unit provided by the present invention is used in the test process. The gate and drain of the MOS device to be tested are respectively connected to one SMU, and the source and base are grounded. By reducing the number of SMUs connected to the MOS device during the test process to two , Under the premise of not increasing the test cost, it can not only effectively prevent mutual interference when multiple devices are tested at the same time, and ensure the accuracy of the measurement, but also connect the redundant SMU to other MOS devices to be tested to realize parallel testing of multiple MOS devices. , improve the test efficiency. |
| priorityDate | 2022-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID409904393 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID65407 |
Total number of triples: 21.