| abstract |
A fully wrapped around gate integrated circuit structure with an attached metal gate and a gate dielectric with a dipole layer is described. For example, an integrated circuit structure includes: a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer over a first gate dielectric, the first gate dielectric comprising a high-k dielectric layer over a first layer of dipole material. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer over a second gate dielectric, the second gate dielectric comprising a high-k dielectric layer over a second layer of dipole material. |