| abstract |
The present disclosure relates to gate structures and methods of forming the same. A device includes: a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate a region overlying the semiconductor layer, wherein a second gate length of the second gate region is equal to the first gate length; and a second spacer on sidewalls of the second gate region, wherein the second spacer The piece is narrower than the first spacer. |