http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113964200-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30655 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2020-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d1646e779e1d9950560efd8480f1fbd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a43990a9dfb3dbec7841ac95c3a4b17 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5c3c94dba6b0eab02f7167cda152578 |
| publicationDate | 2022-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113964200-A |
| titleOfInvention | Semiconductor structure and method for forming semiconductor structure |
| abstract | A semiconductor structure and a forming method of the semiconductor structure are provided, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises an isolation region, and a plurality of mutually discrete fin parts are arranged on the substrate; forming a first dielectric structure on the substrate and on the surface of the fin portion, wherein the first dielectric structure is internally provided with a plurality of grid openings crossing the fin portion, and the grid openings cross the isolation region; forming 1 gate structure in each gate opening; removing the gate structure on the isolation region, and forming a first opening penetrating through the gate structure in the first dielectric structure on the isolation region; removing at least part of the first medium structure between the adjacent first openings, and forming a second opening communicated with the first openings between the adjacent first openings, wherein the first openings and the second openings form a partition opening; and forming a strain layer at least in the partition opening. Thus, the performance and reliability of the semiconductor structure is improved. |
| priorityDate | 2020-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.