| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2021-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d40711f2e9e0cb6974045971628b43f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_896aefdc8098461f13eb77cf82ee2086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b6233a4c496bfd6a9ae1287130e4e6a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4d55a61fef4bebe9e79c2f3a377f005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f181b76dfa2729502b10d4e238c9f6f |
| publicationDate |
2021-11-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113594250-A |
| titleOfInvention |
transistor structure |
| abstract |
The present disclosure is directed to a transistor structure and methods for forming high voltage nanosheet transistors and low voltage wraparound gate transistors on a common substrate. The method includes forming a fin structure on a substrate having a first nanosheet layer and a second nanosheet layer. The method also includes forming a gate structure on the fin structure, having a first dielectric and a first gate electrode, and removing portions of the fin structure not covered by the gate structure. The method also includes partially etching the exposed surface of the first nanoplatelet layer to form a recessed portion in the first nanoplatelet layer of the fin structure and a spacer structure in the recessed portion. Additionally, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure adjacent to the fin structure. |
| priorityDate |
2020-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |