http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111696928-A

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filingDate 2019-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b60506c9aac8654aca5da0a1739e0ade
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publicationDate 2020-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-111696928-A
titleOfInvention Semiconductor package structure and manufacturing method thereof
abstract A semiconductor packaging structure, comprising at least one conductor, a conductive layer, at least one chip and an encapsulant, wherein the conductor is arranged between the conductive layer and the chip and connects the conductive layer to the chip For electrical connection, the encapsulant covers all outer surfaces of the chip. In the present invention, a conductive layer is provided on the temporary carrier board, and at the same time, the conductive layer and the chip are electrically connected through a conductor with a certain height, so that there is a gap between the chip and the conductive layer, so that the encapsulant can wrap the chip. All outer surfaces of the chip are beneficial to avoid the occurrence of chip breakage.
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