| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02219
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0273
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02211
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2019-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_849681db194da1f68557934db8fe36fc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_227a46727c75895be6dddb12e4d97833 |
| publicationDate |
2020-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-110890321-A |
| titleOfInvention |
Method for manufacturing semiconductor structure |
| abstract |
The present disclosure relates to a method of fabricating a semiconductor structure. The method comprises the following steps: a hard mask is deposited. A multi-layer structure is deposited on the hard mask. The multilayer structure includes a bottom layer, a first intermediate layer on the bottom layer, a second intermediate layer on the first intermediate layer, and a top layer on the second intermediate layer. The first intermediate layer includes a hydrocarbon silicon oxide material having a silicon-silicon bond content of about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first intermediate layer, and the patterned first intermediate layer has a plurality of openings. The hard mask is etched through the openings of the patterned first intermediate layer. |
| priorityDate |
2018-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |