| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2027-11866
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0676
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-118
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2018-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2019-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-110582849-A |
| titleOfInvention |
Vertical full ring library architecture |
| abstract |
A system and method for creating a layout of vertical full ring standard cells is described. A metal gate is arranged around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. A gate extension metal (GEM) is disposed over the metal gate at least on the gate contact. A gate via is formed on the GEM at a location where a local interconnect layer can be used to route a gate connection. Arranging local metal layers is used to connect local wiring and power connections. |
| priorityDate |
2017-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |