| abstract |
The invention discloses a wafer-level chip size packaging structure, comprising: an image sensing chip and a chip. The image sensor chip includes a first redistribution layer, wherein the first redistribution layer includes wires and conductive pads, the conductive pads are formed on the wires, and the conductive pads are exposed on the surface of the first redistribution layer. The chip includes a second redistribution layer, wherein the second redistribution layer includes wires and conductive pads, the conductive pads are formed on the wires, and the conductive pads are exposed on the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensing chip, and the chip is bonded to the first redistribution layer of the image sensing chip through the second redistribution layer. |