| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
| filingDate |
2018-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_94e8abc638daae08f99f77b189571e2b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df071dbbdde78f489470fda2c9412854
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8c16e23e0f8eef85460b7d0deb3607d3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_446d391287f263eefdad303c3239212e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cc514cde00ef68616d975b3b66146436 |
| publicationDate |
2019-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109841673-A |
| titleOfInvention |
Semiconductor device and method of manufacturing the same |
| abstract |
A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a gate electrode on the substrate; an upper capping pattern on the gate electrode; and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern includes: a first portion located between the gate electrode and the upper capping pattern; and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. An upper cover pattern covers the topmost surface of each of the second portions. |
| priorityDate |
2017-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |