| abstract |
Disclosed are a parallel structure, a manufacturing method thereof, and an electronic device including the parallel structure. The parallel structure includes alternately stacked source/drain layers and channel layers on a substrate, and gate stacks respectively formed around at least part of the periphery of each channel layer. Each channel layer, the source/drain layers on the upper and lower sides thereof, and the gate stack formed around them constitute a corresponding semiconductor device. In each semiconductor device, one of the source/drain layers on the upper and lower sides of the corresponding channel layer is in contact with the first conductive channel provided on the periphery of the active area, and the other source/drain layer is in contact with the first conductive channel provided on the periphery of the active area. The two conductive channels are in contact with each other, and the gate stack formed around the channel layer is in contact with the third conductive channel provided on the periphery of the active region. The first conductive channel is common to all semiconductor devices, the second conductive channel is common to all semiconductor devices, and the third conductive channel is common to all semiconductor devices. |