| abstract |
The present application relates to semiconductor devices having pillars for stress relief at surface discontinuities and discloses a semiconductor device (100) comprising: a first body (102) having a first coefficient of thermal expansion (CTE) and a first surface (102a); a third body (111) having a third CTE and a third surface (111d) facing the first surface, and an angle relative to the third surface to define the third body (111) a fourth surface of the edge; and a second body (103) having a second CTE higher than the first and third CTEs, the second body (103) contacting the first and third surfaces. A post having a fourth CTE lower than the second CTE traverses the second body and contacts the edge. |