| abstract |
The present invention relates to metal layer wiring levels for vertical FET SRAM and logic cell scaling, providing VFET SRAMs with sub-fin metal wiring layers formed with gates of one transistor pair and bottom S/D connections of another transistor pair or logic device method and resulting device. Embodiments include a pair of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; a conformal liner layer formed over the substrate; an ILD formed over the liner layer a metal wiring layer formed between the pairs of fins, on the lining layer between the first pair and at least on the bottom S/D layer between the second pair, and the upper surface is formed on the active fin below the fins; GAAs formed on dielectric spacers around each fin of the first pair; and bottom S/D contacts xc (cross-coupled) formed on the metal wiring layer adjacent to or through the GAAs, respectively connection) or specialized xc. |