| abstract |
Test architectures, test systems, and methods of testing semiconductor devices at the wafer level are disclosed. A method of fabricating a semiconductor chip from a wafer having a test architecture includes forming a plurality of dice on the wafer, each of the plurality of dice including a semiconductor device, forming at least two common pads generally coupled to the dice, The at least two common pads are formed in a dicing lane that divides the dies from each other, and the semiconductor device is simultaneously tested at the wafer level using the at least two common pads. |