| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66515
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2016-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2019-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-106711042-B |
| titleOfInvention |
Methods and structures for semiconductor mid-line (MEOL) processes |
| abstract |
A method of forming a semiconductor device provides a precursor including a substrate having a first region and a second region, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor also includes a gate stack over the insulator and a gate stack over the channel region. The precursor also includes a first dielectric layer over the gate stack. The method also includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate vias over the gate stack, forming source and drain (S/D) vias over the S/D regions, and forming gate vias over the S/D regions and S/D vias are formed in vias. Embodiments of the present invention also relate to methods and structures for semiconductor mid-line (MEOL) processes. |
| priorityDate |
2015-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |