| abstract |
Techniques for forming vertical transistor architectures are disclosed. According to some embodiments, a semiconductor layer is disposed over an underlying interconnect layer and patterned into a plurality of vertical semiconductor bodies (eg, nanometers) in a regular, semi-regular, or irregular array as desired for a given target application or end use wires and/or other three-dimensional semiconductor structures). Thereafter, according to some embodiments, a gate layer is formed surrounding the active channel portion of each (or some subset) of the vertical semiconductor bodies, followed by an overlying interconnect layer. During processing, a given vertical semiconductor body can optionally be removed and, according to some embodiments, either: (1) emptied to provide dummy channels; or (2) replaced with conductive plugs to provide vias or other layers between wiring. Processing may be performed in multiple iterations, eg, to provide any standard and/or custom constructed multi-level/stacked vertical transistor circuit architecture. |