| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-24195
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-04105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15153
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-24227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01029 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5389
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-16 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-48 |
| filingDate |
2011-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2017-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-104332417-B |
| titleOfInvention |
The preparation method of built-in type semiconductor package |
| abstract |
The present invention discloses a kind of preparation method of built-in type semiconductor package.The semiconductor package part includes semiconductor element, top patterned conductive layer, the dielectric layer between top patterned conductive layer and semiconductor element, the first inner layer electrical articulamentum, underlying patterned conductive layer, via hole and the second inner layer electrical articulamentum with electrical contact.Dielectric layer has the first opening for exposing electrical contact and patterned conductive layer extends to the second opening of top patterned conductive layer from below.The first inner layer electrical articulamentum extends to top patterned conductive layer from electrical contact and is filled in the first opening.Second opening has the upper part for exposing top patterned conductive layer and the lower part for exposing underlying patterned conductive layer.Via hole is located at the lower part of the second opening.Second inner layer electrical articulamentum is filled in the upper part of the second opening. |
| priorityDate |
2010-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |